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ATmega128
Table 104. Boundary-scan Signals for the ADC
Direction
as Seen
Recommended
Input
Output Values when
Recommended Inputs
Signal
from the
when not
are Used, and CPU is
Name
COMP
ACLK
ADC
Output
Input
Description
Comparator Output
Clock signal to gain stages
in Use
0
0
not Using the ADC
0
0
implemented as Switch-
cap filters
ACTEN
Input
Enable path from gain
0
0
stages to the comparator
ADCBGEN
Input
Enable Band-gap
0
0
reference as negative
input to comparator
ADCEN
Input
Power-on signal to the
0
0
ADC
AMPEN
Input
Power-on signal to the
0
0
gain stages
DAC_9
DAC_8
DAC_7
DAC_6
DAC_5
DAC_4
DAC_3
DAC_2
DAC_1
DAC_0
EXTCH
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Bit 9 of digital value to DAC
Bit 8 of digital value to DAC
Bit 7 of digital value to DAC
Bit 6 of digital value to DAC
Bit 5 of digital value to DAC
Bit 4 of digital value to DAC
Bit 3 of digital value to DAC
Bit 2 of digital value to DAC
Bit 1 of digital value to DAC
Bit 0 of digital value to DAC
Connect ADC channels 0 -
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
3 to by-pass path around
gain stages
G10
G20
GNDEN
Input
Input
Input
Enable 10x gain
Enable 20x gain
Ground the negative input
0
0
0
0
0
0
to comparator when true
HOLD
Input
Sample & Hold signal.
1
1
Sample analog signal
when low. Hold signal
when high. If gain stages
are used, this signal must
go active when ACLK is
high.
IREFEN
Input
Enables Band-gap
0
0
reference as AREF signal
to DAC
262
2467X–AVR–06/11
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